(1) Field of the Invention
The invention relates to the manufacturing of high speed, low power consumption, low voltage, and/or high current Integrated Circuit (IC) chips, and, more specifically, to methods of creating fine line interconnections and coarse metal interconnections on top of the fine line interconnections for high speed, low power consumption, low voltage, and/or high current (IC) chips.
(2) Description of the Related Art
When the dimensions of Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
Since the 1960's, sputtered aluminum has become a main stream IC interconnection metal material. The aluminum film is sputtered covering the whole wafer, and then the metal is patterned using photolithography methods and dry and/or wet etching. It is technically difficult and economically expensive to create thicker than 2 μm aluminum metal lines due to the cost and stress concerns of blanket sputtering. About 1995, damascene copper metal became an alternative for IC metal interconnection. In damascene copper, the insulator is patterned and copper metal lines are formed within the insulator openings by blanket electroplating copper and chemical mechanical polishing (CMP) to remove the unwanted copper. Electroplating the whole wafer with thick metal creates large stress and carries a very high material (metal) cost. Furthermore, the thickness of damascene copper is usually defined by the insulator thickness, typically chemical vapor deposited (CVD) oxides, which does not offer the desired thickness due to stress and cost concerns. Again it is also technically difficult and economically expensive to create thicker than 2 μm copper lines.
U.S. Pat. No. 6,495,442 to M. S. Lin et al and U.S. Pat. No. 6,383,916 to M. S. Lin, add, in a post passivation processing sequence, a thick layer of dielectric over a layer of passivation and layers of wide and thick metal lines on top of the thick layer of dielectric.